Date: January 12/13
Lecture: 4
Next lecture HW#4
Status Complete
Code lec04.vhdl
Handout hand04.docx
Lesson SlidesECE_383_Lec4.pptx

Sequential Elements

This lesson has the following goals:

Mod 10 counter example

Truth Table

The following state table defines a straightforward mod 10 counter - a counter that goes from 0-9 and then wraps back around to 0.
clk reset ctrl D Q+
0,1,falling x xx x Q
rising 0 xx x 0
rising 1 00 x Q
rising 1 01 x Q+1 mod 10
rising 1 10 D D
rising 1 11 x 0

Timing Diagram

First, we will fill out the timing diagram on the first page of hand04.docx (linked above). The key idea to remember is that the output of the counter does not change until a positive edge of the clock arrives. On the first 2 rising clock edges, reset is equal to 0 so Q will go to 0. After the second rising clock edge, though, the reset line is never low, so the behavior of the counter is dictated by the last four rows of the state table. On clock edges 3 to 30, ctrl is 01, so Q is incremented by 1. Remember that on the clock edge after Q=9, Q rolls back to 0. The following timing diagram was created in Isim to recreate the timing diagram in the handout.

Circuit Diagram

After completing the timing diagram, see if you can figure out how to construct the counter using the arrangement of devices show in the picture below (also in the hand04.docx document).


As we know, the VHDL description of a circuit consists of two components: the entity and the architecture. The entity is fairly simple, as it consists of those signals in the state table description given at the top of this page - all you need to do is determine the direction and type of the signals. Since 'ctrl' is selecting which operation to perform and is not a numeric value, its type is std_logic_vector. The Q and D outputs are best thought of as numerical values and are consequently unsigned. In order to use these two types, the top of the VHDL file needs to reference both the std_logic_1164 and numeric_std libraries.
The entity description for the mod 10 counter is shown below.
entity lec4 is
	Port(	clk: in  STD_LOGIC;
		reset : in  STD_LOGIC;
		ctrl: in std_logic_vector(1 downto 0);
		D: in unsigned (3 downto 0);
		Q: out unsigned (3 downto 0));
end lec4;
Below, the architecture code for the mod 10 counter is shown. The VHDL code of the mod 10 counter is going to be something new. To break it down, the code consists of three statements: the process (lines 5-23), and the two CSAs (concurrent signal assignments) on lines 24 and 25. The process realizes the circuit you completed above. A few things to note about the code: Note that the condition ctrl = 00 is not assigned a case in the VHDL code. This is because if a signal is not explicitly changed inside a process, then it retains its previous value (similar to software programming languages).
1.  architecture behavior of lec4 is
2.  	signal rollSynch, rollCombo: STD_LOGIC;
3.  	signal processQ: unsigned (3 downto 0);

4.  begin
5.      process(clk)
6. 	begin
7.  	    if (rising_edge(clk)) then
8.  		if (reset = '0') then
9.  		    processQ <= (others => '0');
10.  		    rollSynch <= '0';
11.  		elsif ((processQ < 9) and (ctrl = "01")) then
12.  		    processQ <= processQ + 1;
13.  		    rollSynch <= '0';
14.  		elsif ((processQ = 9) and (ctrl = "01")) then
15.  		    processQ <= (others => '0');
16.  		    rollSynch <= '1';
17.  		elsif (ctrl = "10") then
18.  		    processQ <= D;
19.  		elsif (ctrl = "11") then
20.  		    processQ <= (others => '0');
21.  		end if;
22. 	    end if;
23. 	end process;

24. 	rollCombo  <= '1' when (processQ = 9) else '0';
25. 	Q <= processQ;

26.  end behavior;

General VHDL Rules

Now that we have been working with VHDL for a few lessons, we will introduce the following rules that you must follow when designing in VHDL. The reason for these rules is that following them will help ensure that you write code that can be synthesized. It may be helpful to refer to these rules in the future.

Adding signals in Vivado Simulator

In order to fully understand the behavior of the counter being instantiated inside the testbench, it is sometimes necessary to transcend the design hierarchy and examine signals inside modules not directly visible at the top layer. As an example, let's say you wanted to monitor the control signal into the lab4 counter while running the testbench. This is accomplished in ISim (which has the same functionality as Vivado Simulator) using the following four steps (illustrated in the figure below).
  1. In the Instances and Process subwindow, reveal the instances inside the lec4_tb by clicking on the arrow to the left of lec4_tb.
  2. Reveal the signals inside the lec4 instance (called uut - unit under test) by clicking on the label "uut".
  3. In the Objects subwindow, select the signal that you want to observe on the timing digram. In our case the ctrl signal.
  4. Drag and drop the signal into the timing diagram.
  5. In most cases, you will have to restart the simulation to get a complete trace of the newly added signal.
  6. And then rerun it for the needed amount of time.

More Vivado Simulator Tips

In the Image below, 4 additional details of the Vivado Simulator are pointed out.
  1. This is where simulations are run from in Vivado. You shouldn't have to mess with the default simulation settings for most projects, but you can set the default simulation time here (normally 1000ns).
  2. This is the unit under test, shown as number 2 in the image above.
  3. These two arrows are extremely useful in simulations. The left arrow resets all your signals, while the right signal runs the simulation for the amount of time specified next to the arrow. Since 1000ns would only capture 2 clock cycles of a 500ns clock, you are going to need to run your simulation for more time to see the ctrl signal actually change.
  4. Whenever you rerun your simulation, it is best to use 'fit to window' to see your whole signal chain. From there, you can zoom in and out.