Start date: March 8
End date: March 15
Lab: 3
Status Complete

Lab 3 - Software control of a datapath

Lab Overview

In this lab, we will integrate the video display controller developed in Lab 2 with the MicroBlaze processor built using the fabric of the Artix-7 FPGA. In the preceding lectures, we learned about the Vivado and SDK tool chains, now it's time to put that knowledge to the test by building a software controlled datapath. Lab 2 revealed some shortcomings of our oscilloscope that this lab intends on correcting. Specifically, we will add: The following figure shows required functionality - your program should allow the user to change the position of the triggerVolt and triggerTime indicators with the result that the waveform should be drawn so that the periodic waveform is increasing through that voltage at that time.

In order to accomplish this, you will need to make some minor changes to the lab2 component, create a new piece of IP, and then program that IP using the MicroBlaze, as described in the block diagram below. We will walk through these steps below.

Note: In your program, you will provide a user menu (through the terminal), allowing the user to adjust the trigger voltage and trigger time. Therefore, you may want to check if the user has hit the key on the keyboard without having to actually read the key. For these cases, the following command will prove useful. Note that "uartRegAddr" is a constant, the address of the uart.


With the exception of the following Engineering Change Orders (ECO) in the table below, the hardware you developed in lab2 will be unchanged. For the following ECO, please refer to the high-level architecture in Lab 2.
Name: Trigger Voltage, Trigger Time
Scope: lab2_dp and lab2
Type: Change to the entity descriptions.
  • Inside the lab2_dp component, remove the logic driving the triggerVolt and triggerTime signals into the video component.
  • Remove the buttons signal from the lab2 and lab2_dp entities.
  • Remove the buttons signal from the ucf file.
  • Add the triggerVolt and triggerTime signals to the lab2 and lab2_dp entity descriptions.
  • Drive the triggerTime and triggerVolt inputs on the video component with the corresponding signals on the lab2_dp entity.
Your first step will be to create a component for your lab2 component in your Vivado repository. This will require you to think about what signals are routed to the MicroBlaze and what signals are going outside the Artix 7 chip. The following table should help.
Signals To/From MicroBlaze Signals Going Outside Artix 7
exWrAddr clk
exWen reset
exSel ac_mclk
L_bus_out, R_bus_out ac_adc_sdata
exLbus, exRbus ac_dac_sdata
flagQ ac_bclk
flagClear ac_lrclk
triggerTime sda
triggerVolt scl
ready tmds


Gate Check 1

By the conclusion of lesson 21, you need to have all of your Lab 2 functionality implemented with the Microblaze. That is, you need to export your Lab 2 design into the SDK and be able to achieve the same functionality as you did in Lab 2.

Gate Check 2

By the conclusion of lesson 22, you need to be able to send USART commands using Tera Term (or another terminal emulator) to your FPGA to adjust the trigger on the screen. The trigger on the screen should properly react to moving the trigger either up or down.

Required Functionality

In order to achieve required functionality, you will need to properly trigger the oscilloscope on channel 1 using a positive edge trigger. Control of this process is to be performed using the MicroBlaze. The main tasks of the MicroBlaze will include:

B-level Functionality

A-level Functionality

A-level Functionality

Using one bit from a vector to trigger an interrupt

In order to achieve A functionality, this assignment requires you to use a single bit of Q (the std_logic_vector output from the flag register) as the interrupt signal. This may require you to extract the one bit Q as a separate signal to connect to the MicroBlaze in your block design.


For this lab, README only needs to include evidence of completing Gate Checks 1 and 2, functionality, and A-functionality, along with the date/time achieved.


Item Grade Points Out of Date Due
Gate Check 1 On-Time ------------------------------------------------------------------ Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 10 End of Lesson 21
Gate Check 2 On-Time ------------------------------------------------------------------ Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 10 End of Lesson 22
Required Functionality On-Time ------------------------------------------------------------------ Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 50 COB L23
A Functionality On-Time ------------------------------------------------------------------ Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 15 COB L23
Use of Git / Bitbucket On-Time: 0 ---- Check Minus ---- Check ---- Check Plus ---- Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 5 COB L23
Code Style On-Time: 0 ---- Check Minus ---- Check ---- Check Plus ---- Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 5 COB L23
README On-Time: 0 ---- Check Minus ---- Check ---- Check Plus ---- Late: 1Day ---- 2Days ---- 3Days ---- 4+Days 5 COB L23
Total 100