- Complete your work on green engineering paper
- Staple in upper left if more than one sheet.
- Format the top of the first sheet as follows.
The page reference for the first page of a four page document would be 1/4, the
second page of this document would be labeled 2/4 and so on.
|ECE 383 ||[Your name] ||HW#1 ||[Due Date] ||[Page ref]
- Do not write on the back side of the green engineering paper
- Digital copies of all code, testbenches, and waveforms will also be submitted via BitBucket.
- [3.5] Assume that a is a 10-bit signal with the std_logic_vector(9 downto 0) data type.
List the 10 bits assigned to the a signal.
- a <= (others => '1');
- a <= (1|3|5|7|9 => '1', others => '0');
- a <= (9|7|2 => '1', 6 => '0', 0 => '1', 1|5|8 => '0', 3|4 => '0');
- [3.6] Assume that a and y are 8-bit signals with the std_logic_vector(7 downto 0) data type.
If the signals are interpreted as unsigned numbers, the following assignment statement performs a / 8.
y <= "000" & a(7 downto 3);
- [3.7] Assume the same a as in Problem 3.6. We want to perform a mod 8 and assign the result to y.
Rewrite the previous signal assignment statement using only the & operator.
- Draw a hardware schematic, similar to the one at the end of lecture 3,
for the following circuits. You are given comparators, muxes and adders;
do NOT show the internal organization of these devices. Whenever possible
reduce the number of devices required to realize the design. You should
assume that X, Y, and Z are unsigned(7 downto 0).
- if (X==0) then Z = X else Z = Y
- if (X==Y) then Z = Y else Z = X+Y
- if (X < Y) then Z = X+4 else Z = Y+6
- if (X > Y) then Z = X+5 else Z = X+6
Create a digital circuit that takes as input a 8-bit unsigned value
(provided by the DIP switches) and illuminates an LED if the input
is a multiple of 17. Do NOT use the remainder or division operations,
this can easily be accomplished using a single conditional signal
- A hardcopy (plus digital copy via BitBucket) of your VHDL file (include a proper header).
- A hardcopy (plus digital copy via BitBucket) of a timing diagram from Isim showing several inputs and the output.
- A hardcopy (plus digital copy via BitBucket) of your .xdc file. You may have to add the following line to your .gitignore (!*/**/*.srcs/**/*.xdc)
- Digital copy of your BIT file via BitBucket.
- Demo your circuit in class on LSN 4.